1. Field
This disclosure relates generally to data processing systems, and more specifically, to using one or more metrics for selective BTB allocation.
2. Related Art
Branch target buffers have been used extensively to improve processor performance by reducing the number of cycles spent in execution of branch instructions. Branch target buffers act as a cache of recent branches and accelerate branches by providing either a branch target address (address of the branch destination) or one or more instructions at the branch target prior to execution of the branch instruction, which allows a processor to more quickly begin execution of instructions at the branch target address.
Branch lookahead schemes are also used to accelerate branch processing, and operate by scanning ahead into the sequential instruction stream, looking for upcoming branch instructions in advance of their execution, and computing branch target addresses of branches early, to allow branch target instructions to be fetched in advance of branch instruction execution, in case the branch is taken.
Branch prediction logic may be used with both BTB and branch lookahead schemes to allow for an early prediction of the outcome (taken or not taken) of a conditional branch, prior to the resolution of the branch condition, thus allowing for increased branch performance when accuracy of the predictor is high.
Many current branch target buffer designs use an allocation policy that allocates an entry for every branch instruction encountered in the instruction stream. This approach tends to be inefficient, since not taken branches are likely to be not taken in the future, and allocating an entry for them may displace future taken branch entries, thus lowering the hit rate of the branch target buffer.
Another approach waits to allocate an entry in the branch target buffer until it is known that a branch is actually taken, since a not-taken branch has a high probability of not being taken on the next execution. For larger branch target buffers, this may be a reasonable approach, however, for low-cost systems where the size of the branch target buffer must be minimized, an improved method of allocating new entries in the branch target buffer is desired.